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Product name:

FMN2ET1TCB-25IG

Density:2Gb+1Gb LPD2

NAND ECC: 4bit ECC

P/N:FMN2ET1TCB-25IG

Bus Width:(NAND)X8 (DRAM)x32

Speed:(NAND)25ns (DRAM)800Mbps

PKG(mm):162 BFBGA(8x10.5mm)

Temp:-40℃~85℃

Status:MP

 

Details
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Stacked Multi-Chip Product(MCP) 1.8V NAND Flash Memory and Mobile DDR2
1. MCP Features

• Operating Temperature Range - Industrial Part : -40°C ~ 85°C
• Package Type :

- 162-ball FBGA, 8.05x10.5mm2, 0.8T, 0.5mm Ball Pitch

- Lead & Halogen Free
NAND

• x8/x16 I/O BUS - NAND Interface - ADDRESS / DATA Multiplexing
• SUPPLY VOLTAGE - VCC = 1.8 Volt core supply voltage for Program, Erase and Read operations
• MEMORY CELL ARRAY - x8 : (2K + 64) bytes x 64 pages x 2048 blocks - x16: (1K + 32) words x 64 pages x 2048 blocks
• PAGE READ / PROGRAM - Synchronous Page Read Operation - Random access : 25us (Max) - Serial access : 45ns (1.8V) - Page program time : 300us (Typ)
• ELECTRONIC SIGNATURE - Manufacturer Code - Device Code
• DATA RETENTION - Max cycling: 50K Program / Erase cycles - Data retention: 10 Years(4bit/512byte ECC)
DRAM

- VDD2 = 1.14–1.30V

- VDDCA/VDDQ = 1.14–1.30V

- VDD1 = 1.70–1.95V

- Interface : HSUL_12

- Data width : x16, x32

- Clock frequency : 400 MHz

- Four-bit pre-fetch DDR architecture

- Eight internal banks for concurrent operation

- Multiplexed, double data rate, command/address inputs; commands entered on every CK edge

- Bidirectional/differential data strobe per byte of data(DQS/DQS#).

- DM masks write date at the both rising and falling edge of the data strobe

- Programmable READ and WRITE latencies (RL/WL)

- Programmable burst lengths: 4, 8, or 16

- Auto refresh and self refresh supported

- All bank auto refresh and per bank auto refresh supported

- Clock stop capability

• Low Power Features

- Low voltage power supply.

- Auto TCSR (Temperature Compensated Self Refresh).

- PASR (Partial Array Self Refresh) power-saving mode.

- DPD (Deep Power Down) Mode.

- DS (Driver Strength) Control.

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